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Diagnosing and Fixing a Page Fault Performance Issue With Arm64 Atomics Oct 24th 2025, 12:00 by Dave Neary While running a synthetic benchmark that pre-warmed the cache, we noticed an abnormal performance impact on Ampere CPUs. Digging deeper, we found that there were many more page faults happening with Ampere CPUs when compared to x86 CPUs. We isolated the issue to the use of certain atomic instructions like ldadd, which load a register, add a value to it, and store data in a register in a single instruction. This triggered two "page faults" under certain conditions, even though this is logically an all-or-nothing operation, which is guaranteed to be completed in one step. In this article, we will summarize how to qualify this kind of problem, how memory management in Linux works in general, explain how an atomic Arm64 instruction can generate multiple page faults, and show how to avoid performance slowdowns related to this behavior.

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